Common mode feedback amplifiers

Skip to search form Skip to main content Skip to account menu You are currently offline. Some features of the site may not work correctly. DOI: They allow evaluation of the conversion gain or linear interaction, relative performance, and nonlinear interaction between common-mode and differential-mode loops in any fully differential one-stage output compensated amplifier. Three often used CMFB loops, based on different operation principles, are classified according to these figures of merit. View on IEEE.

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• Low-Power Variable Gain Amplifier Free of Common-Mode Feedback Circuit
• A high open loop gain common mode feedback technique for fully differential amplifiers
• PRIORITY DATA
• Minimum mode configuration of 8086 microprocessor (Min mode)
• EP 2466745 A1 20120620 - Amplifier common-mode control methods
• Best Tl072

WATCH RELATED VIDEO: 8 FullyDifferential opamp

Low-Power Variable Gain Amplifier Free of Common-Mode Feedback Circuit

Effective date : Year of fee payment : 4. Techniques for performing frequency compensation of common-mode feedback loops for differential amplifiers are disclosed. Operational amplifiers having a differential output require an accurate common-mode feedback loop in order to set the common-mode output voltage of the amplifier.

The error signal is fed back into the main amplifier, and the common-mode of the amplifier is set equal to the reference voltage. The error is therefore eliminated. In a typical common-mode feedback circuit, the common-mode voltage is sensed and compared to a reference by a differential pair. The resulting common-mode error signal is fed back to the operational amplifier by means of a current mirror.

Often this conventional common-mode feedback implementation does not have enough gain, particularly in sub-micron processes. Thus, in the case of such processes, a common-source gain stage can be added. This type of configuration, however, is associated with problems relevant to frequency compensation.

For example, the loop is compensated by introducing a zero in the loop transfer function at the gate of the common-source gain stage. The capacitor of the zero is physically large, and therefore occupies a large die area. In addition, the bandwidth of the loop is considerably decreased due to the zero. What is needed, therefore, are improved techniques for performing frequency compensation of common-mode feedback loops for differential amplifiers.

One embodiment of the present invention provides a circuit for performing frequency compensation of a common-mode feedback loop for a differential amplifier. The circuit comprises a sensing network operatively coupled to a differential output of the differential amplifier, for sensing a common-mode voltage output by the differential amplifier.

A comparing network e. A current inverter is operatively coupled to the differential sensing circuit for inverting the error signal.

A gain stage is operatively coupled to the current inverter and the differential amplifier for providing a gain adjusted error signal to the differential amplifier. A pole-split network e. Another embodiment of the present invention provides a method for performing frequency compensation of a common-mode feedback loop for a differential amplifier. The method comprises sensing a common-mode voltage output by a differential amplifier using a sensing network, comparing the sensed common-mode voltage with a reference to provide a common-mode error signal to the differential amplifier via a feedback path including a gain stage, and compensating for changes in the frequency characteristic of the common-mode feedback loop due to the gain stage using a pole-split network.

The present invention provides an improvement over conventional common-mode feedback loops for differential amplifiers that use pole-zero cancellation techniques by including a pole-split network in the common-mode feedback loop. The pole-split network enables the use of smaller capacitors in the circuit design, resulting in a robust design that is tolerant to parameter variations and also allows the common-mode feedback loop to have a high bandwidth.

The features and advantages described herein are not all-inclusive and, in particular, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the figures and description. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and not to limit the scope of the inventive subject matter.

The feedback circuit includes a common-mode sensing circuit , a differential sensing circuit , a current inverter , a pole-split network and a gain stage The common-mode sensing circuit is coupled to the outputs of a differential amplifier , for sensing the common-mode voltage of the differential amplifier The common-mode sensing circuit is coupled to the differential sensing circuit and provides the differential sensing circuit with the sensed common-mode voltage.

The differential sensing circuit compares the common-mode voltage with a reference voltage and generates an error signal in response to a difference between the common-mode voltage and the reference voltage. The error signal is provided to the differential amplifier via current inverter and gain stage The feedback circuit can be adapted to provide voltage feedback with voltage subtraction, current feedback with current subtraction, voltage feedback with current subtraction and current feedback with voltage subtraction.

Preferably, the current inverter has low input impedance and high output impedance and an inverting current transfer between the input and the output. The error signal received by the differential amplifier is used to null out the common-mode voltage. The pole-split network is coupled between the common-mode sensing circuit and the current inverter and compensates the common-mode loop by splitting the two dominant poles of the feedback circuit to provide a single pole frequency response.

In one embodiment of the present invention, the common-mode sensing circuit can be a pair of resistors, the differential sensing circuit can be a differential pair, the current inverter can be current mirror, the gain stage can be a common-source stage and the pole-split network can be a capacitor, as described below with respect to FIG.

Alternatively, the pole-split network can include active inversion components, allowing the current inverter to be removed or replaced with a conventional current source e. Depending on the devices used for the active inversion, the pole-split network can be reconfigured to adjust for changes in the frequency characteristics of the loop. The common-mode feedback circuit includes a differential amplifier 10 having its differential output coupled to a sensing network C 1 , C 2 , R 0 , and R 1.

In one embodiment, the loop is compensated using a pole-split network comprising a feedback capacitor C 0 , which is connected between the common-mode sense node designated VCM and the current mirror Note that this compensation scheme avoids problems associated with conventional loop compensation techniques where a zero is introduced at the gate of the common-source gain stage The differential amplifier 10 can be a conventional differential amplifier.

Likewise, the resistor, capacitors, and transistors can each be implemented with generally available components. The specific types of components and their respective ratings will vary depending on factors such as the intended application, and the desired level of performance and accuracy. One skilled in the art will understand the above values are merely provided as an example, and the present invention is not intended to be limited to any one configuration. Generally, there is an unlimited number of other configurations and component combinations that can be implemented in accordance with the principles of the present invention as will be understood by one skilled in the art.

One application for a common-mode feedback circuit configured in accordance with the present invention includes, for example, line drivers for xDSL modems e. Other applications will be apparent in light of this disclosure e. The differential amplifier 10 mimics the input stage of the amplifier , while the voltage sources V 1 and V 2 mimic typical class-AB control circuits.

A pole-split network comprising a feedback capacitor C 0 is connected between the common-mode sense node and the current mirror provides loop compensation. Again, variations on this configuration will be apparent in light of this disclosure, and the present invention is not intended to be limited to any one configuration. For example, the sensing network can be replaced by other sensing circuits e.

Likewise, the differential pair can be replaced by other comparison circuits, such as comparators or be augmented with cascodes. In addition, although the feedback path illustrated in FIG. Components types and values will vary depending on the particular application and desired performance.

The operation of the frequency compensation technique can be understood as follows. The common-source stages , , together with the output stages , , of the amplifier , form a two-stage amplifier for the common-feedback loop. This loop introduces two dominant poles in the loop transfer function, one contributed by the output of the amplifier C 5 , C 6 , R 0 , and R 1 , and the other contributed by the gates of the output transistors M 5 through M 8 C 1 through C 4 , respectively.

Note that the pole contributed by the output of the amplifier is formed by the common-mode load resistance and capacitor combination. In particular, the pole at the positive output Vop is formed by R 0 and C 5 , while the pole at the negative output Von is formed by R 1 and C 6.

Note that the Miller capacitors, C 1 -C 4 , are also used for compensating the signal path of the amplifier In general, the value of capacitors C 1 -C 4 is determined by the signal path. Hence, the required unity-gain frequency needs to be set by the transconductance of the common-source stages , Closing the outer loop with the differential pair , introduces another dominant pole at the gates of the common-source stages , Hence, a system with two dominant poles is provided. These two dominant poles are split by the additional capacitor, C 0 , and a single pole response results.

It is assumed that the zero introduced by the parallel connection of R 0 and C 5 is much higher e. In order not to interfere with the frequency response of the common-mode loop, this pole is dimensioned such that it is at much higher e. If the latter condition is not fulfilled, complex poles might arise thereby resulting in an undesired peaking. However, these poles can be damped by putting a small capacitor e.

One advantage associated with embodiments of the present invention is that the Miller capacitor, C 0 , can be relatively small and the bandwidth of the common-mode loop can be relatively large as compared to conventional techniques. For example, compared to a zero compensation configuration, capacitor area can readily be reduced by a factor of 5 to 10, even when an additional damping capacitor is necessary to minimize undesired peaking.

In addition, this compensation scheme is more robust against parameter variations than conventional configurations. Here, the pole-split network is split into two components, and is represented by capacitors C 0 and C 3 e. These two capacitors are connected to the differential outputs, Von and Vop, respectively. In this way, the common-mode sense resistors R 0 and R 1 are bypassed which gives an enhanced frequency response for some applications.

Such bypassing may be desirable, for example, in applications where the common-mode resistors R 0 and R 1 are large, such as in amplifiers driving a purely capacitive load e. This embodiment employs a combination between two techniques, conventional zero compensation and feedback compensation in accordance with the principles of the present invention.

A portion of the frequency compensation is accomplished by the pole-split network e. In one example embodiment, R 3 is approximately ohms and C 3 is 5 pF. Example values of the other components are as previously indicated. This combinational approach can provide enhanced frequency performance for some applications since the zero can provide additional phase margin.

Such applications might include, for example, those where a high bandwidth in the common-mode loop is needed, or where the common-mode voltages are changing rather quickly, in class-G amplifiers.

In general, note that the zero will be at higher frequencies than in conventional techniques. As such, the value of capacitor C 3 can be smaller than in a conventional configuration, and therefore requires less physical space in the circuit. In addition note that, if the resistor R 3 is set to zero, capacitor C 3 serves as damping capacitor to prevent undesired peaking as previously discussed.

Embodiments of the present invention can be implemented in a number of ways. For example, the disclosed techniques for performing frequency compensation of common-mode feedback loops for differential amplifiers can be implemented in an integrated circuit, chip set, or other discrete package using a variety of IC processes e. Likewise, the disclosed techniques can be implemented on a printed circuit board or line card e.

Other implementations will be apparent in light of this disclosure. The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

What is claimed is: 1. A circuit for performing frequency compensation of a common-mode feedback loop for a differential amplifier, the circuit comprising:. The circuit of claim 1 , wherein the gain stage comprises at least one common-source gain stage. The circuit of claim 1 , wherein the comparing network comprises a differential pair.

A high open loop gain common mode feedback technique for fully differential amplifiers

All rights reserved. Performance n Slew rate: 1. Boldface limits apply at the temperature extremes. Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.

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View PDF. Welcome Guest. Register Forgot Password? Abstract This paper presents an enhanced two stage fully differential op-amp with common mode feedback that achieves improved dc gain, common mode rejection ratio and speed of the op-amp. Two stage op-amp implemented using the telescopic cascode amplifier and common source amplifier. Telescopic operational Op-amp has higher gain, higher pole frequency and lower power dissipation than other configuration and common source amplifier used as transconductance amplifier that help to achieve specification with lower tail current. A high gain, high speed and wide output swing CMOS fully differential operational amplifier is designed using 0. In addition nulling resistor compensation is used to cancel the second pole which is implemented by a MOSFET operating in deep triode region. Finally we conclude that the fully differential Op-amp has many advantages over the single ended counterparts thus it can used in many application like analog to digital convertor, rail to rail design, and other analog IC design.

Minimum mode configuration of 8086 microprocessor (Min mode)

An effective technique to increase the signal swing and reduce noise is to use fully-differential -circuits. However, design of a common-mode feedback CMFB circuit that stabilizes the common-mode output level is essential. In this paper, a general description is given to fully-differential amplifiers with their CMFB loops, then a new error amplifier that is just composed of transistors and stabilizes the DC output level is proposed. We designed a simple and efficient bias circuit that allows the stability and maximum input swing.

EP 2466745 A1 20120620 - Amplifier common-mode control methods

Effective date : Year of fee payment : 4. Techniques for performing frequency compensation of common-mode feedback loops for differential amplifiers are disclosed. Operational amplifiers having a differential output require an accurate common-mode feedback loop in order to set the common-mode output voltage of the amplifier. The error signal is fed back into the main amplifier, and the common-mode of the amplifier is set equal to the reference voltage.

Best Tl072

When a current is injected into a body, in addition to the voltage profile developed on the surface, a common-mode voltage CMV which produces errors in the measurement also appears. The great accuracy needed to reconstruct images in electrical impedance tomography EIT requires the use of differential amplifiers with a high common-mode rejection ratio CMRR to avoid this error. Nevertheless, the effective CMRR is lower than the differential amplifier ratio due to mismatches in the electrode impedances and other circuits in the measurement channel. The stability of the feedback loop is analysed for a broadband system. Simulation and experimental results show that it is possible to obtain an improvement of 40 dB in the measurements at frequencies of up to 10 kHz. Abstract When a current is injected into a body, in addition to the voltage profile developed on the surface, a common-mode voltage CMV which produces errors in the measurement also appears.

A fully differential OTA circuit, as in Figure However, this type of symmetrical circuit needs an extra feedback loop. The feedback around a single- ended OTA usually only provides a differential-mode feedback and is ineffective for common-mode signals. The need for a CMFB circuit is a drawback since it counters many of the advantages of the fully differential approach.

EP A1 EN. EP A Systems and methods for providing a fully differential amplifier performing common-mode voltage control having reduced area and power requirements are disclosed. The amplifier A1 disclosed comprises an additional input stage 30 at the amplifier input which senses the common mode voltage of the amplifier's inputs and applies internal feedback control Zfbkp, Zfbkn to adjust the output common-mode voltage until the input common-mode voltage matches a target voltage Vcmref and thereby indirectly set the output common-mode voltage. Furthermore the internal common-mode control can be implemented in such a manner as to provide a feed-forward transconductance function in addition to common-mode control if desired.

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This paper presents an instrumentation amplifier for ECG signals, compared with the traditional three op amp ECG read instrumentation amplifier, the circuit overcomes the disadvantage of low common mode rejection ratio due to resistance mismatch of the three operational amplifier. At the same time, the circuit uses the inverting integral amplifier as an DC offset feedback circuit to eliminate the offset voltage at the input of the amplifier. This circuit implements the class-AB control circuit to achieve high linearity output.